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www.gennum.com gs9076 hd-linx? iii sd-sdi automatic reclocker with dual differential outputs gs9076 data sheet 44617 - 1 january 2008 1 of 25 features ? smpte 259m-c compliant ? automatic lock to sdi and dvb-asi at 270mb/s ? 4:1 input multiplexe r patented technology ? choice of dual reclocked data outputs or one data output and one recovered clock output ? loss of signal (los) output ? lock detect output ? on-chip input and output termination ? differential 50 inputs and outputs ? mute, bypass and autobypass functions ? footprint and drop-in compatible with existing gs2975a designs ? pb-free and rohs compliant ? single 3.3v power supply ? operating temperature range: 0c to 70c applications ? smpte 259m-c serial digital interfaces description the gs9076 is an sd-sdi serial digital reclocker designed to automatically recover the embedded clock from a digital video signal and re-time the incoming video data. the device autom atically detects and locks to incoming smpte 259m-c sdi and dvb-asi signals at 270mb/s. the gs9076 removes the high frequency jitter components from the bit-serial stream. input termination is on-chip for seamless matching to 50 transmission lines. the device requires only one external crystal to set the vco frequency when not locked and provides adjustment free operation. in systems which require passing of non-smpte data rates, the gs9076 can be configured to either automatically or manually enter a bypass mode in order to pass the signal without reclocking. the gs9076 offers a choice of dual reclocked data outputs or one data output and one recovered clock output. the device is footprint and drop-in compatible with existing gs2975a desi gns, with no additional application changes required. the gs9076 is pb-free, and the encapsulation compound does not contain halogenated flame retardant. this component and all homogeneous sub-components are rohs compliant.
gs9076 data sheet 44617 - 1 january 2008 2 of 25 functional block diagram gs9076 functional block diagram xtal+ xtal- xtal out- xtal out+ ddi_sel[1:0] ddi 1 ddi 2 ddi 3 ddi 0 lf+ lf- kbb ddo_mute ddo 0 autobypass bypass ld auto/man ss[2:0] xtal osc buffer data buffer vco bypass logic divider phase frequency detector divider control logic charge pump m u x d a t a m u x m u x re-timer phase detector sd rco_mute rco/ddo1 clock/data buffer los m u x data/clock l
gs9076 data sheet 44617 - 1 january 2008 3 of 25 contents features ....................................................................................................................... .1 applications................................................................................................................... 1 description .................................................................................................................... 1 functional block diagram .............................................................................................2 1. pin out ..................................................................................................................... .4 1.1 gs9076 pin assignment ...... .............. .............. .............. .............. ........... ........4 1.2 gs9076 pin descriptions .. .............. .............. .............. .............. .............. ........5 2. electrical characteristics ...........................................................................................8 2.1 absolute maximum ratings ............................................................................8 2.2 dc electrical characteristics ............... ...........................................................8 2.3 ac electrical characteristics .............. .............................................................9 2.4 solder reflow profiles ...................................................................................12 3. input / output circuits ............................ .................................................................13 4. detailed description .................................. ..............................................................16 4.1 slew rate phase lock loop (s-pll) .. .........................................................16 4.2 vco ..............................................................................................................17 4.3 charge pump ................................................................................................17 4.4 frequency acquisition loop ? the phas e-frequency detector ..................18 4.5 phase acquisition loop ? the phase detector ...........................................18 4.6 4:1 input mux ................................................................................................19 4.7 automatic and manual data rate select ion .................................................19 4.8 bypass mode ................................................................................................20 4.9 lock and los ...............................................................................................20 5. typical application circuit .......................................................................................21 6. package & ordering information .............................................................................22 6.1 package dimensions ....................................................................................22 6.2 recommended pcb footprint ............. .............. ............ ........... ........... .........23 6.3 packaging data .............................................................................................24 6.4 marking diagram ...........................................................................................24 6.5 ordering information .....................................................................................24 7. revision history ......................................................................................................25
gs9076 data sheet 44617 - 1 january 2008 4 of 25 1. pin out 1.1 gs9076 pin assignment figure 1-1: 64-pin qfn ddi0 nc 64-pin qfn (top view) 1 ddi0_vtt ddi0 gnd ddi1 ddi1_vtt ddi1 gnd ddi2 ddi2_vtt ddi2 gnd ddi3 ddi3_vtt ddi3 gnd lf+ nc nc nc nc nc xtal- xtal+ xtal_out- xtal_out+ gnd vee_ddo vcc_ddo rsv gnd_drv vee_rco vcc_rco rco/ddo1 rsv rco/ddo1 kbb ddi_sel0 ddi_sel1 bypass autobypass vcc_vco vee_vco locked ss0 ss1 ss2 los vcc_dig vee_dig gnd vcc_cp vee_cp nc ddo0 ddo0 16 17 32 33 48 49 64 2 3 4 5 6 7 8 9 10 11 12 13 14 15 18 19 20 21 23 24 25 26 27 28 29 30 31 22 34 35 36 37 38 39 40 41 42 43 44 45 46 47 50 51 52 53 54 55 56 57 58 59 60 61 62 63 lf- ground pad (bottom of package) nc auto ? ? ? ? ddo_mute sd gs9076 ? rco_mute data/clock
gs9076 data sheet 44617 - 1 january 2008 5 of 25 1.2 gs9076 pin descriptions table 1-1: pin descriptions pin number name type description 1, 3 ddi0, ddi0 input serial digital differential input 0. 2 ddi0_vtt passive center tap of two 50 on-chip termination resistors between ddi0 and ddi0 . 4, 8, 12,16, 32, 43, 49 gnd passive recommended connect to gnd. 5, 7 ddi1,ddi1 input serial digital differential input 1. 6 ddi1_vtt passive center tap of two 50 on-chip termination resistors between ddi1 and ddi1 . 9, 11 ddi2, ddi2 input serial digital differential input 2. 10 ddi2_vtt passive center tap of two 50 on-chip termination resistors between ddi2 and ddi2 . 13, 15 ddi3, ddi3 input serial digital differential input 3. 14 ddi3_vtt passive center tap of two 50 on-chip termination resistors between ddi3 and ddi3 . 17, 18 ddi_sel[1:0] logic input serial digital input select. 19 bypass logic input bypass the reclocker stage. when bypass is high, it overwrites the autobypass setting. 20 autobypass logic input automatical ly bypasses the re clocker stage when the pll is not locked this pin is ignored when bypass is high. 21 auto logic input auto select. this pin should be set high for automatic sd-sdi and dvb-asi standard detection. 22 vcc_vco power most positive power supply connection for the internal vco section. connect to 3.3v. 23 vee_vco power most negative power supply connection for the internal vco section. connect to gnd. 24, 25, 26 ss[2:0] bi-directional the ss[2:0] pins will disp lay 010 when the internal pll has locked to a 270mb/s input data rate. 27 nc no connect not connected internally. 28 locked output lock detect. this pin is set high by the device when the pll is locked. ddi_sel1 ddi_sel0 input selected 0 0 ddi0 0 1 ddi1 1 0 ddi2 1 1 ddi3
gs9076 data sheet 44617 - 1 january 2008 6 of 25 29 los output loss of signal. set high when there are no transitions on the active ddi[3:0] input. 30 vcc_dig power most positive power supply connection for the internal glue logic. connect to 3.3v. 31 vee_dig power most negative power supply connection for the internal glue logic. connect to gnd. 33 sd output this signal will be set high w hen the reclocker has locked to 270mbps or low when a non-smpte standard is applied. (i.e. the device is not locked). 34 kbb analog input controls the loop bandwidth of the pll. 35 rco_mute power serial clock or secondary data output mute. assert low for reduced power consumption, see section 2.2 dc electrical characteristics . when rco_mute = low, the rco/ddo1 output is powered down. when rco_mute = high, the rco/ddo1 output is active. note: this is not a logic input pin. 36 ddo_mute logic input mutes the ddo0 and/or rco/ddo1 outputs. 37 data/clock logic input data/clock select. when set high, the rco/ddo1 pin will outpu t a copy of the serial digital ouput (ddo0). when set low, the rco/ddo1 pin will output a re-timed clock (rco). 38, 40 rco/ddo1 / rco/ddo1 output serial clock or secondary data output. when rco_mute is connected to vcc, the serial digital differential clock or secondary data output will be presented. 39, 45 rsv reserved do not connect. 41 vcc_rco power most positive power suppl y connection for the rco/ddo1 and rco/ddo1 output driver. connect to 3.3v. table 1-1: pin descriptions (continued) pin number name type description ddo_mute rco_mute data/clock ddo0 rco/ddo1 11 0dataclock 1 1 1 data data 0 1 0 mute clock 01 1mutemute 1 0 x data power down 0 0 x mute power down note: mute = outputs latched at previous data bit. power down = outputs pulled to v cc through 50 resistor.
gs9076 data sheet 44617 - 1 january 2008 7 of 25 42 vee_rco power most negative power supply connection for therco/ddo1 and rco/ddo1 output driver. connect to gnd. 43 gnd_drv passive recommended connect to gnd. 44, 46 ddo0 , ddo0 output differential serial digital outputs. 47 vcc_ddo power most positive power supply connection for the ddo0/ddo0 output driver. connect to 3.3v. 48 vee_ddo power most negative power supply connection for the ddo0/ddo0 output driver. connect to gnd. 50, 51 xtal_out+, xtal_out- output differential outputs of the referenc e oscillator used for monitoring or test purposes. 52, 53 xtal+, xtal- input reference crystal input. connect to the go1535 as shown in the typical application circuit on page 21 . 54 - 59 nc no connect not connected internally. 60 vee_cp power most negative power supply c onnection for the internal charge pump. connect to gnd. 61 vcc_cp power most positive power supply connecti on for the internal charge pump. connect to 3.3v. 62, 63 lf+, lf- passive loop filter capaci tor connection. connect as shown in the typical application circuit on page 21 . 64 nc no connect not connected internally. recommended connect to gnd. ? center pad ? ground pad on bottom of package. solder to main ground plane following recommendations under recommended pcb footprint on page 23 table 1-1: pin descriptions (continued) pin number name type description
gs9076 data sheet 44617 - 1 january 2008 8 of 25 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics parameter value supply voltage range -0.5v to +3.6 v dc input voltage range v ee - 0.5v to v cc + 0.5v operating temperature range -20c to 85c storage temperature range -50c < t s < 125c input esd voltage 4kv hbm, 100v mm solder reflow temperature 260c note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these condi tions or at any other condition beyond those indicated in the ac/dc electrical char acteristic sections is not implied. table 2-1: dc electrical characteristics v cc = 3.3v 5%, t a = 0c to 70c, unless otherwise shown. typical values: v cc = 3.3v and t a =25c parameter symbol conditions min typ max units supply voltage v cc operating range 3.135 3.3 3.465 v supply current i cc rco/dd01 enabled ? 142 170 ma i cc rco/ddo1 disabled ? 123 152 ma power consumption ? rco/dd01 enabled ? 468 590 mw ? rco/dd01 disabled ? 404 528 mw logic inputs ddi_sel[1:0], bypass, autobypass, auto, ddo_mute v ih high 2.0 ? ? v v il low ? ? 0.8 v logic outputs sd, locked, los v oh i oh = -2ma 2.4 ? ? v v ol i ol = 2ma ? ? 0.4 v bi-directional pins (auto mode) ss[2:0], auto = 1 v oh i oh = -2ma 2.4 ? ? v v ol i ol = 2ma ? ? 0.4 v xtal_out+, xtal_out- v oh high ? v cc - 0.075 ? v v ol low ? v cc - 0.300 ? v
gs9076 data sheet 44617 - 1 january 2008 9 of 25 2.3 ac electrical characteristics rco_mute ? i = -1.5ma v cc - 0.165 v cc v cc + 0.165 v serial input voltage ? common mode 1.65 + (v sid /2) ?v cc - (v sid /2) v serial output voltage ddo0/ddo0 , rco/ddo1 / rco/ddo1 ? common mode ? v cc - (v od /2) ? v table 2-1: dc electrical characteristics (continued) v cc = 3.3v 5%, t a = 0c to 70c, unless otherwise shown. typical values: v cc = 3.3v and t a =25c parameter symbol conditions min typ max units table 2-2: ac electrical characteristics v cc = 3.3v 5%, t a = 0c to 70c, unless otherwise shown. typical values: v cc = 3.3v and t a =25c parameter symbol conditions min typ max units notes serial input data rate ? ? ? 270 ? mb/s ? serial input jitter tolerance ? worst case modulation (e.g. square wave modulation) 0.8 ? ? ui ? pll lock time - asynchronous t alock ??0.52.0ms? pll lock time - synchronous t slock kbb = float, clf=47nf, 270mb/s ? 5 20 us ? serial output rise/fall time sdo0 and rco/ddo1 (20% - 80%) t rsdo ,t rrco 50 load (on chip) ? 110 ? ps ? t fsdo ,t frco 50 load (on chip) ? 110 ? ps ? serial digital input signal swing v sid differential with internal 100 input termination see figure 2-1 100 ? 800 mv p-p ? serial digital output signal swing ddo0 and rco/ddo1 v od 100 load differential see figure 2-2 300 450 600 mv p-p ? ddo0 to ddo1 skew dd skew 270mb/s ? 156 ? ps 1 ddo0 to rco skew dr skew 270 mb/s ? 37 ? ps 2 serial output jitter on ddo0 and ddo1 t oj 270 mb/s ? 0.02 0.07 ui 3 additive jitter t aj bypass mode, 270 mb/s ? 15 ? ps ?
gs9076 data sheet 44617 - 1 january 2008 10 of 25 loop bandwidth bw loop 270 mb/s, kbb = vcc ? 0.16 ? mhz ? 270 mb/s, kbb = float ? 0.32 ? mhz ? 270 mb/s, kbb = gnd, <0.1db peaking ?0.64 ? mhz ? notes: 1. ddo0 to ddo1 skew allignment as defined here: 2. ddo0 to rco skew allignment as defined here: 3. kbb = float, prn = 2 23 -1, input jitter = 40ps p-p table 2-2: ac electrical characteristics (continued) v cc = 3.3v 5%, t a = 0c to 70c, unless otherwise shown. typical values: v cc = 3.3v and t a =25c parameter symbol conditions min typ max units notes ddo0 ddo1 dd skew ddo0 rco dr skew
gs9076 data sheet 44617 - 1 january 2008 11 of 25 figure 2-1: serial digita l input signal swing figure 2-2: serial digital output signal swing v sid v sid 2 v sid 2 v sid 2 + 0 v sid 2 _ v sid 2 v cc _ v sid 2 v cc _ v cc v dd single-ended swing (ddix) single-ended swing (ddix) differential swing (ddix-ddix) v od v od 2 v od 2 v od 2 + 0 v od 2 _ v od 2 v cc _ v od 2 v cc _ v cc v dd single-ended swing (ddo0, ddo1, rco) single-ended swing (ddo0,ddo1, rco) differential swing (ddo0-ddo0) (ddo1-ddo1) (rco-rco)
gs9076 data sheet 44617 - 1 january 2008 12 of 25 2.4 solder reflow profiles the device is manufactured with matte-sn te rminations and is compatible with both standard eutectic and pb-free solder re flow profiles. msl qualification was performed using the maximum pb-free reflow profile shown in figure 2-3 . the recommended standard pb reflow profile is shown in figure 2-4 . figure 2-3: maximum pb-free solder reflow profile (preferred) figure 2-4: standard pb solder reflow profile 25?c 150?c 200?c 217?c 260?c 250?c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3?c/sec max 6?c/sec max 25?c 100?c 150?c 183?c 230?c 220?c time temperature 6 min. max 120 sec. max 60-150 sec. 10-20 sec. 3?c/sec max 6?c/sec max
gs9076 data sheet 44617 - 1 january 2008 13 of 25 3. input / output circuits figure 3-1: ttl inputs figure 3-2: loop filter figure 3-3: crystal input v ref lf+ lf- 5k 10p 250r 250r 5k xtal+ xtal-
gs9076 data sheet 44617 - 1 january 2008 14 of 25 figure 3-4: crystal output buffer figure 3-5: serial data outp uts, serial clock outputs figure 3-6: kbb 1k 1k xtal out- xtal out+ 50 rco/ddo1 ddo0 / rco/ddo1 50 kbb v th2 v th1
gs9076 data sheet 44617 - 1 january 2008 15 of 25 figure 3-7: indicator outputs: sd, locked, los figure 3-8: standard select/indication bi-directional pins figure 3-9: serial data inputs 24k ss[2:0] auto/man 50 ddi[3:0] ddi[3:0] 1k 1k 50 ddi_vtt
gs9076 data sheet 44617 - 1 january 2008 16 of 25 4. detailed description the gs9076 is a sd-sdi serial digital reclocker designed to automatically recover the embedded clock from a digital video signal and re-time the incoming video data. the gs9076 will recover the embedded clock signal and re-time the data from a smpte 259m-c compliant digital video signal. using the functional block diagram ( page 2 ) as a guide, slew rate phase lock loop (s-pll) on page 16 to lock and los on page 20 describes each aspect of the gs9076 in detail. 4.1 slew rate phase lock loop (s-pll) the term ?slew? refers to the output phase of the pll in response to a step change at the input. linear plls have an output phase response characterized by an exponential response whereas an s-pll?s output is a ramp response (see figure 4-1 ). because of this non-linear response characteristic, traditional small signal analysis is not possible with an s-pll. figure 4-1: pll characteristics 0.2 0.1 0.0 input output slew pll response phase (ui) 0.2 0.1 0.0 input output linear (conventional) pll response phase (ui)
gs9076 data sheet 44617 - 1 january 2008 17 of 25 the s-pll offers several advantages over the linear pll. the loop bandwidth of an s-pll is independent of the transition density of the input data. pseudo-random data has a transition density of 0.5 ve rses a pathological signal which has a transition density of 0.05 . the loop bandwidth of a linear pll will change proportionally with this change in transition density. with an s-pll, the loop bandwidth is defined by the jitter at the data input. this translates to infinite loop bandwidth with a zero jitter input signal. this allows the loop to correct for small variations in the input jitte r quickly, resulting in very low output jit ter. the loop bandwidth of the gs9076?s pll is defined at 0.2ui of input jitter. the pll consists of two acquisition loops. first is the frequency acquisition (fa) loop. this loop is active when the device is not locked and is used to achieve lock to the supported data rates. second is the phase acquisition (pa) loop. once locked, the pa loop tracks the incoming data and makes phased corrections to produce a re-clocked output. 4.2 vco the internal vco of the gs9 076 is an lc oscillator. it is trimmed at the time of manufacture to capture all data rates over temperature and operation voltage ranges. integrated into the vco is a series of programmable dividers used to achieve all serial data rates, as well as additional dividers for the frequency acquisition loop. 4.3 charge pump during frequency acquisition, the charge pump has two states, ?pump-up? and ?pump-down,? which is produced by a leading or lagging phase difference between the input and the vco frequency. during phase acquisition, there are two levels of ?pump-up? and two levels of ?pump down? produced for leading and l agging phase difference between the input and vco frequency. this is to allow for greater precision of vco control. the charge pump produces these signal s by holding the integrated frequency information on the external loop-filter capacitor, c lf . the instantaneous frequency information is the result of the curren t flowing through an internal resistor connected to the loop-filter capacitor.
gs9076 data sheet 44617 - 1 january 2008 18 of 25 4.4 frequency acquisition loop ? the phase-frequency detector an external crystal of 14.140 mhz is us ed as a reference to keep the vco centered at the last known data rate. this allows the device to achieve a fast synchronous lock, especially in cases where a known data rate is interrupted. the crystal reference is also used to clock internal timers and counters. to keep the optimal performance of the reclocker over all ope rating conditions, the crystal frequency must be 14.140 mhz, +/-50ppm. the go 1535 meets this specification and is available from gennum. the vco is divided by a selected ratio which is dependant on the input data rate. the resultant is then compared to the crystal frequency. if the divided vco frequency and the crystal frequency are within 1% of each other, the pll is considered to be locked to the input data rate. 4.5 phase acquisition loop ? the phase detector the phase detector is a digital quadrature phase detector. it indicates whether the input data is leading or lagging with respect to a clock that is in phase with the vco (i-clk) and a quadrature clock (q-clk). when the phase acquisition loop (pa loop) is locked, the input data transition is aligned to the falling edge of i-clk and the output data is re-timed on t he rising edge of i-clk. during high input jitter conditions (>0.25ui), q-clk will sample a different value than i-clk. in this condition, two extra phase correction signals will be generat ed which instructs the charge pump to create larger frequency corrections for the vco. figure 4-2: phase detector characteristics when the pa loop is active, the crystal frequency and the incoming data rate are compared. if the resultant is more that 2%, the pll is considered to be unlocked and the system jumps to the fa loop. i-phase alignment edge data re-timing edge q-phase alignment edge 0.25ui 0.8ui i-clk q-clk input data with jitter re-timed output data
gs9076 data sheet 44617 - 1 january 2008 19 of 25 4.6 4:1 input mux the 4:1 input mux allows the connection of four independent streams of video/data. there are four differential inputs (ddi[3:0] and ddi[3:0] ). the active channel can be selected via the ddi_sel[1:0] pins. table 4-1 shows the input selected for a given state at ddi_sel[1:0]. the ddi inputs are designed to be dc interfaced with the output of the gs9074a cable equalizer. there are on chip 50 termination resistors which come to a common point at the ddi_vt pins. connect a 10nf capacitor to this pin and connect the other end of the capacitor to ground. this terminates the transmission line at the inputs for optimum performance. if only one input pair is used, connect t he unused positive inputs to +3.3v and leave the unused negative inputs floating. this helps to eliminate crosstalk from potential noise that would couple to the unused input pair. 4.7 automatic and manual data rate selection the gs9076 can be configured to manua lly lock to a specific data rate or automatically search for and lock to the incoming data rate. the auto/man pin selects automatic data rate detection mode (auto mode) when high and manual data rate selection mode (manual mode) when low. in auto mode, the ss[2:0] bi-directional pins become outputs and the bit pattern indicates the data rate that the pll is locked to (or previously locked to). in manual mode, the data rate can be programmed and the ss[2:0] pins become inputs. in this mode, the pll will on ly lock to the data rate selected. table 4-2 shows the ss[2:0] pin settings for either the data rate selected (in manual mode) or the data rate that the pll has locked to (in auto mode). table 4-1: bit pattern for input select ddi_sel[1:0] selected input 00 ddi0 01 ddi1 10 ddi2 11 ddi3 table 4-2: data rate indication/selection bit pattern ss[2:0] data rate (mb/s) 010 270
gs9076 data sheet 44617 - 1 january 2008 20 of 25 4.8 bypass mode in bypass mode, the gs9076 passes the data at the inputs directly to the outputs. there are two pins that control the bypass function: bypass and autobypass. when bypass is set high, the gs9076 will be in bypass mode. when autobypass is set high, the gs90 76 will be configur ed to enter bypass mode only when the pll has not locked to a data rate. when bypass is set high, autobypass will be ignored. when the pll is not lo cked, and both bypass and autobypass are set low, the serial digital output ddo0/ddo0 or ddo1/ddo1 will produce invalid data. 4.9 lock and los the locked signal is an active high output which indicates when the pll is locked. the internal lock logic of the gs9076 includes a system which monitors the frequency acquisition loop and the phase acquisition loop as well as a monitor to detect harmonic lock. the los (loss of signal) output is an ac tive high output which indicates the absence of data transitions at the ddix inpu t. in order for this output to be asserted, transitions must not be present for a period of t la = 5 - 10 us. after this output has been asserted, los will deassert within t ld = 0 - 5 us after the appearance of a transition at the ddix input. figure 4-3: los signal timing note: los is sensitive to transitions appearing at the input, and does not distinguish between transitions caused by input data, and transitions due to noise. data los t la t ld
gs9076 data sheet 44617 - 1 january 2008 21 of 25 5. typical application circuit figure 5-1: gs9076 typical application circuit ddi_sel1 ddo_mute ddi_sel0 locked sd 3.3v 3.3v 3.3v 3.3v 10n 10n 10n 10n 47n gs9076 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ddi0 ddi0_vt ddi0 gnd ddi1 ddi1_vt ddi1 gnd ddi2 ddi2_vt ddi2 gnd ddi3 ddi3_vt ddi3 gnd ddi_sel0 ddi_sel1 bypass autobypass auto vcc_vco vee_vc0 ss0 ss1 ss2 nc locked los vcc_dig vee_dig gnd sd kbb ddo_mute rco_mute rsv rco/ddo1 vcc_rco vee_rco gnd_drv ddo0 rsv ddo0 vcc_ddo vee_ddo gnd xtal_out+ xtal_out- xtal+ xtal- nc vee_cp vcc_cp lf- lf+ nc 10n (14.140mhz) 10n 10n 10n data input 1 data input 0 data input 3 data input 2 data output zo = 50 zo = 50 zo = 50 zo = 50 zo = 50 3.3v 10n 100 go1535 note: all resistors in ohms and all capacitors in farads. nc nc nc nc nc rco/ddo1 clock output zo = 50 los rco_mute data/clock data/clock
gs9076 data sheet 44617 - 1 january 2008 22 of 25 6. package & ordering information 6.1 package dimensions a b 9 . 00 4 . 50 4 . 50 9 . 00 2x 2x 0 .1 5 c 0 .1 5 c 0 .1 0 c 0 . 08 c 6 4 x s eatin g plan e 0 . 90 + / - 0 .1 0 +0 . 03 0 . 0 2- 0 . 02 0 .2 0 re f c 7 .1 0 + / - 0 .1 5 3 . 55 0 .4 0 + / - 0 . 05 7 .1 0 + / - 0 .1 5 3 . 55 0 .2 5 + / - 0 . 05 6 4 x 0 .1 0 c a b c 0 . 05 0 . 50 a ll dimen s i o n s in m m pin 1 area centre tab 0 . 35 45 4 ? 45 5 ? 0 . 3 + / - 0 . 05
gs9076 data sheet 44617 - 1 january 2008 23 of 25 6.2 recommended pcb footprint the center pad of the pcb footprint should be connected to the ground plane by a minimum of 36 vias. note: suggested dimensions only. final dimensions should conform to customer design rules and process optimizations. note: all dimensions are in millimeters. 7.10 7.10 8.70 8.70 0.50 0.25 0.55 center pad
gs9076 data sheet 44617 - 1 january 2008 24 of 25 6.3 packaging data 6.4 marking diagram 6.5 ordering information parameter value package type 9mm x 9mm 64-pin qfn moisture sensitivity level (per jedec j-std-020c) 3 junction to case thermal resistance, j-c 9.1c/w junction to air thermal resistance, j-a (at zero airflow) 21.5c/w junction to board thermal resistance, j-b 5.6c/w psi, 0.2c/w pb-free and rohs compliant yes gs9076 xxxxe3 yyww pin 1 id xxxxe3 yyww yyww - date code yy - 2-digit year ww - 2-digit week number xxxx - l ot/work order id part number package temperature range gs9076 GS9076-CNE3 pb-free 64-pin qfn 0c to 70c
caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 gennum japan corporation shinjuku green tower building 27f, 6-14-1, nish i shinjuku, shinjuku-ku, tokyo, 160-0023 japan tel. +81 (03) 3349-5501, fax. +81 (03) 3349-5505 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. the sale of the circuit or device described herein does not imply any patent license, and gennum makes no representation that the circuit or device is free from patent infringement. gennum and the g logo are registered trademarks of gennum corporation. ? copyright 2007 gennum corporation. all rights reserved. printed in canada. www.gennum.com gs9076 data sheet 44617 - 1 january 2008 25 25 of 25 document identification data sheet the product is in production. gennum reserves the right to make changes to the product at any time wit hout notice to improve reliability, function or design, in order to provide the best product possible. 7. revision history version ecr pcn date changes and/or modifications 1 149009 ? january 2008 changes to functional block diagram , figure 3-7 and ordering information . addition of section 4.7 automatic and manual data rate selection . 0 144926 ? may 2007 new document.

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